The challenge facing ArTile,formerly the microprocessor engineering division of Toshiba America Electronic Components Inc.,was born of a triumph.The group had created the MIPS-based Emotion En-gine chip,the processing heart of the Sony Playstation 2.Toshiba believed that the work,whose outcome had proved so successful for Sony,could be spun into more gold by turning the design team into an independent business -sort of MIPS-based systems-on-chip while you wait.

But that left the newly independent ArTile Microsystems with a tall order: Come up with a methodology capable of quickly floor planning and developing systems-on-chip based on the MIPS core.

The problems were clear.Such SoC devices would vary considerably in on-chip functional blocks and in floor plans.While all blocks,including the CPU, were synthesizable,some were too large to be handled by existing synthesis tools,and some were above the ideal size for the team's place and route tools. So designs would have to be done hierarchically,and that hierarchy would have to be based on tool limitations rather than on architectural features.

ArTile's response to the problem was twofold:a physical partitioning scheme and a proprietary tool development.

The partitioning scheme was relatively simple.The design would be divided into blocks small enough to accommodate the synthesis,placement and routing tools.The blocks would be defined with fixed contact locations at their edges and would be abutted.

Signals passing from one block to an adjacent block would simply be stitched across the several-channel gap between the blocks;the spacing would prevent unwanted interactions between traces in adjacent blocks.Connections between nonadjacent blocks would be passed daisychain fashion from block to block until they reached their destination.

Thus,global routing consisted entirely of stitching together contacts lying directly across from each other,across the gaps between blocks.

That sounds great in theory,but it assumes very careful partitioning and construction of the indi- vidual blocks.Too small,and the design becomes unmanageable again.Too large,and the individual blocks may become uncontrollable.Wrong partitioning choices,and the level of traffic between blocks becomes unwieldy.

Enter the second element:the proprietary partitioning and floor-planning tool.The team devel- oped an interactive tool that could examine a complex-block netlist;identifying the inputs,outputs, critical paths and areas of congestion;and assisting in separating the netlist into smaller blocks. Those smaller blocks,with their fixed contact locations, are what ArTile calls tiles.The tool can also assist in re- shaping a tile as the floor plan evolves,working around fixed-size hard marcos within the tile.Tiles inherit the clock regions and timing constraints of the larger blocks from which they were carved.

In effect,the floor planner transforms the functionally hierarchical netlist,organized into blocks such as CPU, caches,bus controllers and the like,into an entirely different hierarchy based on tool capacity and routing ease.From that point on,the design is handled at two levels:as a collection of independent tiles and as a full, flattened chip.

The tiles are sufficiently small that the entire synthe- sis,place,route,verification and extraction tool set can be traversed relatively quickly.The MIPS CPU core decomposes into four tiles,for example.That makes it possible to work on logic errors,timing closure,clock synthesis,power routing and the like within the manageable confines of the tile. And should the floor plan change,the moving of contacts or the reshaping of the tile are manageable problems.

Verification proceeds at both the tile and chip levels. Obviously,any changes within a tile mean reverification for that tile.Nothing else changes unless contact locations have to shift.

But the ArTile team also reverifies at the chip level and does a full-chip static timing analysis at the end of each iteration.That process is accelerated by the logical and electrical separability of the tiles and by the fact that verification and STA runs exist for unaltered tiles.

So far,the methodology is proving out in practice. Using the interactive floor-planning tool,the team can do multiple floor plans in a single day,yielding lots of room for exploration.

The sticking point in the methodology is still timing closure,where the results remain highly dependent on tool choices.The team is experimenting with a number of physical synthesis tools in place of conventional synthesis at the tile level as a way of reducing the timing- closure headaches.

Overall,ArTile thinks it has achieved the flexibility it needed.The team has taken an ambitious design from RTL lockdown to final STA in as little as two weeks.That kind of throughput means that iterations reaching clear back to logic design can be accommodated,and it is not necessary to throw the passengers overboard to avoid late-stage logic changes.

As an illustration,on a recent 6 million-gate design, the team was compelled to make a significant RTL change one week from scheduled tapeout.Confining the changes to a tile and reworking at the tile and full-chip levels,the team achieved tapeout three weeks after the changes were initiated.

With first-time working silicon in hand and a new standard-product processor to show the world, ArTile is enthusiastic about its approach.

In addition to the MIPS-related tiles,the team is incorporating IP from parent Toshiba and is licensing some outside IP and partitioning it into the tile library.

Shardul Kazi is chief operating officer and Andy Le is director of physical design and methodology at ArTile Microsystems,in San Jose,Calif.